View SSC1S311A_9077047.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

quasi - r esonant off - line switching control ics SSC1S311A data sheet SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 1 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 description SSC1S311A is the controller ic of a quasi - resonant mode for a switching power supplies. th e ic incorporates a startup circuit an d a standby function to reduce a power consumption and standby power. in normal operation, the quasi - resonant mode operation achieves high efficiency and low noise. in addition, in medium to low load conditions, the operation mode is automatically changes the quasi - resonant mode to the bottom - skip mode to improve efficiency. the ic is p rovide d in the soic8 package . th e power supply that is a low component counts and a high performance - to - cost can be achieved by t he rich set of pr otection features . features multi - mode control ( high e fficiency o peration in all r ange of l oads ) automatic standby function ( standby p ower is inproved by b urst o scillation m ode ) i nput p ower at no load : <30mw at 100vac <50mw at 230 vac bottom - skip function ( switching l oss in m edium to l ow l oads is reduced) step - on burst oscillation function ( transformer a udible n oise s are reduced) bias assist fu nction s oft - s tart f unction adjustable startup voltage m aximum o n - time l imit ation function v cc o perational r ange e xpanded l eading e dge b lanking (leb) f unction ( e xternal f ilter c omponents are reduced) protection f unctions overcurrent protection (ocp) : pulse - by - pulse overvoltage protection (ovp) : auto - restart overload protection (olp) : auto - restart thermal shutdown (tsd) : auto - restar t typical application vac c 1 d 2 r 2 c 2 t 1 d 4 c 6 r 6 r 7 u 2 r 9 r 11 c 7 d p s pc 1 pc 1 c 4 r ocp d 1 r 8 r 10 l 1 c 8 c v v ou t gnd 1 2 4 gnd v cc bd fb / olp st ocp drv 8 7 6 5 ssc 1 s 311 a u 1 d 3 r 5 r 4 r 3 q 1 c 3 r bd 2 r bd 1 dz bd c bd r 1 c 5 r 12 c 9 r st package s soic8 not to scale specifications v cc maximum rating: 35 v o peration start voltage, v cc(on) : 15.1 v ( typ. ) pwm operation frequency, f osc : 21.0 khz ( typ. ) maximum on - time, t on (max) : 40.0 s ( typ. ) application s digital appliance office a utomation (oa) e quipment white g oods industrial a pparatus communication f acilities
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 2 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 contents description ------------------------------------------------------------------------------------------------------ 1 contents --------------------------------------------------------------------------------------------------------- 2 1. absolute maximum ratings ----------------------------------------------------------------------------- 3 2. electrical characteristics -------------------------------------------------------------------------------- 4 3. block diagram --------------------------------------------------------------------------------------------- 6 4. pin configuration definitions --------------------------------------------------------------------------- 6 5. typical applications -------------------------------------------------------------------------------------- 7 6. physical dimensions -------------------------------------------------------------------------------------- 8 7. marking diagram ----------------------------------------------------------------------------------------- 8 8. operational description --------------------------------------------------------------------------------- 9 8.1. startup operation ----------------------------------------------------------------------------------- 9 8.1.1. startup pe riod --------------------------------------------------------------------------------- 9 8.1.2. undervoltage lockout (uvlo) circuit --------------------------------------------------- 9 8.1.3. bias assist function --------------------------------------------------------------------------- 9 8.1.4. auxiliary winding -------------------------------------------------------------------------- 10 8.1.5. soft - start function -------------------------------------------------------------------------- 11 8.1.6. operational mode at startup ------------------------------------------------------------- 11 8.2. constant voltage control operation ---------------------------------------------------------- 12 8.3. quasi - resonant operation and bottom - on timing --------------------------------------- 13 8.3.1 . quasi - resonant operation ---------------------------------------------------------------- 13 8.3.2. bottom - on timing -------------------------------------------------------------------------- 13 8.3.3. bd pin blanking time --------------------------------------------------------------------- 15 8.3.4. bottom skip quasi - resonant operation ----------------------------------------------- 16 8.4. auto standby function --------------------------------------------------------------------------- 17 8.5. overvoltage protection (ovp) ------------------------------------------------------------------ 18 8.6. overload protection (olp) ---------------------------------------------------------------------- 18 8.7. thermal shutdown (tsd) ----------------------------------------------------------------------- 19 8.8. overcurr ent protection (ocp) ----------------------------------------------------------------- 19 8.8.1. overcurrent input compensation function ------------------------------------------- 19 8.8.2. reference bd pin peripheral components setting ----------------------------------- 21 8.8.3. reference example of no overcurrent input compensation required ---------- 22 8.9. maximum on - time limitation function ---------------------------------------------------- 22 8.10. drv pin peripheral components -------------------------------------------------------------- 22 9. design notes ---------------------------------------------------------------------------------------------- 23 9.1. peripheral components -------------------------------------------------------------------------- 23 9.2. transformer design ------------------------------------------------------------------------------ 23 9.3. protection against negative input voltage at start - up pin ------------------------------- 25 9.4. phase compensation ------------------------------------------------------------------------------ 25 9.5. pcb trace layout and component placement ----------------------------------------------- 26 important notes ---------------------------------------------------------------------------------------------- 28
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 3 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 1. absolute maximum ratings current polarities are defined as follows: current going into the ic (sinki ng) is positive current (+); current coming out of the ic (sourcing) is negative current (?). unless otherwise specified, t a = 25 c. parameter s ymbol conditions pins rating unit supply voltage of control part v cc 7 ? 8 35 v startup pin voltage v st 4 ? 8 ? 0.3 to 600 v ocp pin voltage v ocp 6 ? 8 ? 2.0 to 6.0 v fb pin voltage v fb 1 ? 8 ? 0.3 to 7.0 v fb pin current i fb 1 ? 8 10.0 ma bd pin v oltage v bd 2 ? 8 ? 6.0 to 6.0 v allowable power dissipation p d D 0.14 w operating ambient t emperature t op D ? 40 to 125 c storage temperature t stg D ? 40 to 125 c junction temperature t j D 150 c
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 4 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 2. electrical characteristics current polarities a re defined as follows: current going into the ic (sinki ng) is positive current (+); current coming out of the ic (sourcing) is negative current (?). unless specifically noted, t a = 25 c, v cc = 20 v. parameter symbol conditions pins min. typ. max. unit po wer supply startup operation operation start voltage v cc(on) 7?8 13.8 15.1 17.3 v operation stop voltage ( 1 ) v cc(off) 7?8 8.4 9.4 10.7 v circuit current in operation i cc(on) 7?8 D 1.3 3.7 ma circuit current in non - operation i cc(off) v cc = 13 v 7?8 D 4.5 50 a startup circuit operation voltage v start(on) 4?8 18 21 24 v startup current i cc(startup) v cc = 13 v 7?8 ? 4.5 ? 3.1 ? 1.0 ma startup current supply threshold voltage (1) v cc(bias) 7?8 9.5 11.0 12.5 v pwm operation frequency f osc 5?8 18. 4 21.0 24.4 khz soft - start operation period t ss 5?8 D 6.05 D ms normal operation bottom - skip operation threshold voltage 1 v ocp(bs1) 6?8 0.487 0.572 0.665 v bottom - skip operation threshold voltage 2 v ocp(bs2) 6?8 0.200 0.289 0.380 v quasi - re sonant operation threshold voltage 1 ( 2 ) v bd(th1) 2?8 0.14 0.24 0.34 v quasi - resonant operation threshold voltage 2 (2) v bd(th2) 2?8 0.07 0.17 0.27 v maximum feedback current i fb(max) 1?8 ? 320 ? 205 ? 120 a standby operation standby operation th reshold voltage v fb(stbop) 1?8 0.45 0.80 1.15 v protect ion operation maximum on - t ime t on(max) 5?8 30.0 40.0 50.0 s leading edge blanking time t bw 5?8 D 495 D ns overcurrent detection threshold voltage (normal operation) v ocp(h) 6?8 0.820 0. 910 1.000 v overcurrent detection threshold voltage (input compensation in operation) v ocp(l) v bd = ? 3 v 6?8 0.560 0.660 0.760 v bd pin current i bd(o) v bd = ? 3 v 2?8 ? 250 ? 83 ? 30 a olp bias current i fb(olp) v fb/olp = 5v 1?8 ? 15 ? 10 ? 5 a olp threshold voltage v fb(olp) 1?8 5.50 5.96 6.40 v circuit current after olp i cc(olp) 7?8 D 575 D a v cc pin ovp threshold voltage v cc(ovp) 7?8 28.5 31.5 34.0 v fb pin maximum voltage in feedback operation v fb(max) i fb = ? 12a 1?8 3.70 4.05 4.40 v (1) v cc(bias) > v cc(off) (2) v bd(th1) > v bd(th2)
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 5 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 parameter symbol conditions pins min. typ. max. unit thermal shut d own temperature t j(tsd) D 135 D D c drive circuit drv pin output voltage v drv 5?8 7.5 8.1 8.7 v drv pin source current (peak) i drv(so) 5?8 D ? 150 D ma drv pin sink current (peak) i drv(si) 5?8 D 608 D ma therm al c haracteristics ther mal resistance j-a D D D 180 c /w
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 6 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 3. block diagram 4. pin configuration definitions 1 5 6 7 8 4 2 fb / olp bd st drv ocp gnd v cc 3 number name function 1 fb/olp constant voltage control, s tandby control, and overload detection signal inp ut 2 bd bottom detection and i nput compensation signal input 3 D ( pin removed ) 4 st startup current input 5 drv gate drive output 6 ocp overcurrent detection signal input 7 v cc supply voltage input and o vervoltage detection signal input 8 gnd ground uvlo reg/iconst logic drv fb/stb olp ocp/bs startup osc bd v cc 7 gnd 8 4 st 5 drv 6 ocp 1 fb/olp 2 bd
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 7 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 5. typical application s the startup voltage of figure 5 - 1 is about 21v which is startup circuit operation voltage , v start(on) . when the startup voltage increases more than this, figure 5 - 2 is available, adding dz st in series with the st pin. the startup voltage after adding dz st , v start(on) ? is calculated as follows: zst ) on ( start ) on ( start v v ' v + =
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 8 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 6. physical dimensions notes: - dimensions in millimeters - bare lead frame: pb - free ( rohs compliant) 7. marking diagram 1 8 part number s c 1 s 3 1 1 s k y m d a c ontrol n umber lot number : y is the last digit of the year of manufacture ( 0 to 9 ) m is the month of the year ( 1 to 9 , o , n , or d ) d is the period of days represented by : 1 : the first 10 days of the month ( 1 st to 10 th ) 2 : the second 10 days of the month ( 11 th to 20 th ) 3 : the last 10 ? 11 days of the month ( 21 st to 31 st )
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 9 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 8. operational description all the characteristic value s given in this section are typical values, unless they are specified as minimum or maximum. current polarities are defined as follows: current going into the ic (sinking) is positive current (+); current coming out of the ic (sourcing) is negative current (?). 8.1. startup operation 8.1.1. startup period figure 8 - 1 shows v cc pin peripheral circuit. the built - in startu p circuit is connected to the st pin , and it generates a constant current, i cc(startup) = ? 3. 1 ma, to charge cap acitor c 2 con nected to the v cc pin. during this process, when the v cc pin voltage reaches v cc(on) = 15. 1 v, t he control circuit starts opera tion. after that, the startup circuit stops automatically, in order to eliminate its own power consumption. the appro ximate startup time, t start , is calculated as follows: ) cc(startup cc(int) cc(on) start i v v c2 t , ( 1 ) where: t start is the startup time in s, and v cc(int) is the initial voltage of the v cc pin in v. vac c 1 d 2 r 2 c 2 t 1 d p d 1 v cc gnd st 4 8 7 u 1 v d r st figure 8 - 1 . v cc p in p eriheral c ircuit 8.1.2. undervoltage lockout (uvlo) circuit figure 8 - 2 shows the relationship of v cc and i cc . when the v cc pin voltage increases to v cc(on) = 15. 1 v, the control circuit starts oper ation and th e circuit current, i cc , increases . in operation, when the v cc pin voltage decreases to v cc(off) = 9.4 v, the control circuit stop s operation, by the uvlo (under voltage lockout) circuit, and rever ts to the state before startup. the voltage rectified the au xiliary winding voltage, v d , in figure 8 - 1 becomes a power source to the control circuit after the operation start. the v cc pin voltage should become as follows within the specification of input voltage range and the output load range of power supply, taking account of the winding turns of the d winging. the target voltage of the v cc pin voltage is about 20 v. ) v )( v ( 5 . 28 v ) v )( v ( 5 . 12 min ) ovp ( cc cc max ) bias ( cc < < , ( 2 ) circuit current , i cc i cc on =3.7ma max off 15.1v v cc on v cc pin voltage start stop figure 8 - 2 . v cc vs . i cc 8.1.3. bias assist function figure 8 - 3 shows the v cc pin voltage behavior during the startup period. when the v cc pin voltage reaches v cc(on) = 15. 1 v, the control circuit starts operation, the circuit current, i cc , increases , and thus the v cc pin voltage begins dropping. at the same time, the auxiliary winding voltage, v d , increases in proportion to the output voltage rise. thus, the v cc pin voltage is set by the balance between dropping by the increase of i cc and rising by t he increase of the auxiliary winding voltage, v d . just at the turning - off of the power mosfet, a surge voltage occurs at the output winding. if the feedback control is activated by the surge voltage under light load condition at startup, and the v cc pin vo ltage decreases to v cc(off) = 9.4 v, a startup failure can occur, because the output power is restricted and the output voltage decreases. in order to prevent this, during a state of operating feedback control (that is, the fb/olp pin
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 10 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 voltage is v fb(stbop) = 0.8v or less) , when the v cc pin voltage falls to the startup current supply threshold voltage , v cc(bias) = 11.0 v, the bias assist function is activated. while the bias assist function is operating, the decrease of the v cc pin voltage is suppressed by pro viding the startup current, i cc( startup ) , from the startup circuit . by the bias assist function, the use of a small value c2 capacitor is allowed, resulting in shortening startup time. also, because the increase of v cc pin voltage becomes faster when the o utput runs with excess voltage, the response time of the ovp function can also be shortened. it is required to check and adjust the process so that poor starting conditions may be avoided. figure 8 - 3 . v cc during s tartup p eriod 8.1.4. auxiliary winding in actual switch - mode power supply (smps) circuits, there are cases in which the v cc pin voltage fluctuates in proportion to the output of the smps (see figure 8 - 4 ), and the overvoltage protection (ovp) on v cc pin may be activated. this happens because c2 is charged to a peak voltage on the auxiliary winding d, which is caused by the transient surge voltage coupled from the primary winding when the power mosfet turn s off. for alleviating c2 peak charging, it is effective to add some value r2, of several tenths of ohms to several ohms, in series with d2 (see figure 8 - 5 ). the optimal value of r2 should be determined using a transformer matchi ng what will be used in the actual application, because the variation of the auxiliary winding voltage is affected by the transformer structural design. figure 8 - 4 . v cc versus i out with / without resistor r2 u 1 v cc gnd 7 8 c 2 r 2 d 2 d added figure 8 - 5 . v cc pin peripheral circuit with r2 the variation of v cc pin voltage becomes worse if: the c oupling between the primary and secondary windi ngs of the transformer gets worse and the surge voltage increases (low output voltage, large current load specification, for example). the coupling of the auxiliary winding , d , and the secondary side stabilization output winding (winding of the output line which is controlling constant voltage ) gets worse and it is subject to surge voltage. in order to reduce the influence of surge voltages on the v cc pin, alternative structures of the auxiliary winding, d, can be used as examples of transformer structural designs see figure 8 - 6 . winding structural example (a) - separating the auxiliary winding d from the primary side windings p1 and p2. - the primary side winding is divided into two windings, p1 and p2. winding structural example ( b ) - placing the auxiliary winding d within the secondary winding s1 in order to improve the coupling of those windings. - the output winding s1 is a stabilized output winding controlled to constant voltage.
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 11 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 figure 8 - 6 . winding s tructure example 8.1.5. soft - start function figure 8 - 7 shows the behavior of v cc pin voltage and the drain current during the startup period. the ic activates the soft - start function during the startup period. the soft - start operation period , t ss , is in ternally set to 6.05 ms, and the overcurrent protection (ocp) th reshold voltage steps up in four steps during this period. this reduces the voltage and current stres s on the power mosfet and on the secondary - side rectifier. during the soft - start operation period, the operation is in pwm operation with pwm operation frequency of f osc = 21.0 khz. in addition, because the soft - start operation period is fixed internally, it is necessary to conf irm and adjust the v cc pin voltage and the overload protection (olp) delay time during startup , based on actual operation in the application. 8.1.6. operational mode at startup as shown in figure 8 - 8 because the auxiliary winding voltage is low at startup, there is a certain period when the quasi - resonant signal has not yet reached a regulat ed level (quasi - resonant operation threshold voltage 1, v bd(th1) , is 0.24 v or more, and the effective pulse width for t he quasi - resonant signal is 1.0 s or more). during this period, the operation is in pwm operation with pwm operation frequency of f osc = 21.0 khz. then, when the output voltage rises, the auxiliary winding voltage will rise, and when a quasi - resonant signal reaches the regulated level, quasi - resonant operation will begin. in addition, during the soft - start operation period, t ss , the operation is in pwm operation, even if the quasi - resonant signal reaches the regulated level. figure 8 - 7 . operational mode in startup winding s tructur e example (a) winding s tructure example (b) d s1 p2 s2 p1 p core bobbin s 1 p2 p1 s1 d s2 barrier tape pin side barrier tape p1 , p2 : primary winding s1: secondary winding of which the output voltage is controlled constant s2: secondary winding d : a uxiliary winding for v cc core bobbin
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 12 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 8.2. constant voltage control operation the constant output voltage control function uses the current mode control (peak current mode), which enhances response speed and provides stable operation. this ic compares the voltage, v rocp , of a current detection resistor with the target voltage, v sc , by the internal fb comparator, and controls the peak value of v rocp so that it gets close to v sc . v sc is internally generated from the fb/olp pin voltage ( see figure 8 - 8 and figure 8 - 9 ). light l oad c onditions when load conditions become lighter, the output voltage, v out , rises, and the feedback current from the error amplifier on the secondary side also increases . the feedback current is sunk at the fb/olp pin, transferred through a photo - coupler, pc1, and the fb/olp pin voltage decreases. thus, v sc decreases and the peak value of v rocp are controlled to be low, and the peak drain current of i d decreases. this con trol prevents the output voltage from increasing. heavy l oad c onditions when load conditions become greater, the control circuit performs the inverse operation to that described above. thus, v sc increases and the peak drain current of i d increases. this co ntrol prevents the output voltage from decreasing. pc 1 c 3 r ocp 6 8 1 ocp fb / olp gnd u 1 i fb v rocp r 12 c 9 q 1 figure 8 - 8 . fb / olp peripheral circuit v sc fb comparator drain current , i d - + - - - - - - for the pcb trace layout of the current detection resistor, r ocp , see section 9.5 . match the turn - on timing to a v ds bottom point. lower the value of the voltage resonant capacitor, c v , and the value of the capacitor in the secondary side snubber circuit. add a cr filter with r12 and c9 to the ocp pin as s hown in figure 8 - 8 . the cr filter should be determined according to the surge voltage level. it is necessary to check and adjust the cr filter values because they change the ocp detection level and the load condition switched to burst oscillation mode at standby. when the cr filter is unnecessary, make r12 short and c9 open. when it is added, the targ et value of r12 is 100 to 330 , and that of c9 is 470pf to 680pf. v ocp(h) ' of figure 8 - 10 is the overcurr ent detection threshold voltage after input compensatio n in section 8.8 . surge voltage width in turning - off t bw v ocp ( h ) ' figure 8 - 10. ocp pin voltage waveform
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 13 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 8.3. quasi - resonant operation and bottom - on timing 8.3.1. quasi - resonant operation figure 8 - 11 shows the circuit of a flyback converter. a flyback converter is a system which transfers the energy stored in the transformer to the secondary side when the primary side power mosfet is turned off. after the energy is completely trans ferred to the secondary, when the mosfet keeps turning off, the mosfet drain node begins free oscillation based on the l p of the transformer and c v across the drain and source pins. the quasi - resonant ope ration is the v ds bottom - on operation that turns - on the mosfet at the bottom point of v ds free oscillation. figure 8 - 12 shows an ideal v ds waveform during bottom - on operation. using bottom - on operation, switching loss and switchi ng noise are reduced and it is possible to obtain converters with high efficiency and low noise. this ic performs bottom - on operation not only during normal quasi - resonant operation, but also during bottom - skip quasi - resonant operation. this allows reducti on of the o peration frequency during light load conditions, to improve efficiency across the full range of loads. t 1 s e in n p n s l p c v e fly i d i off v ou t c 6 v f c 1 d 4 p figure 8 - 11. basic f lyback c onverter c ircuit in figure 8 - 11, symbols means as follows: e in : input voltage e fly : flyback voltage ( ) f ut o s p fly v v n n e + = n p : primary side number of turns n s : secondary side number of turns v out : output voltage v f : forward voltage drop of the secondary side rectif ier i d : drain current of power mosfet i off : s econdary side rectifier flowing c urrent during the power mosfet is off c v : voltage resonant capacitor l p : primary side inductance v ds 0 i off 0 i d 0 t on e in e fly t on dly : half cycle of free oscillation bottom point figure 8 - 12. ideal bottom - on operation waveform ( power mosfet turn - on at a bottom point of a v ds waveform) 8.3.2. bottom - on timing figure 8 - 13 shows the voltage waveform of the bd pin peripheral circuit and auxiliary winding, d. the follow ing setup is required with the bd pin . bottom - on timing setup (described here, below) ocp input compensation value setup ( see section 8.8 ) the components dz bd , r bd1 , r bd2 , and c bd , are connected to the bd pin peripheral circuit as shown in figure 8 - 13 , with values that are determined with the above - mentioned steps 1 ) and 2 ) . this delay time , t ondly , for bottom - on, from the start of v ds free oscillation to the timing of turning - on the power mosfet, is cr eated by exploiting the auxiliary winding voltage, which synchronizes to the drain voltage v ds waveform. the voltage on e ither end of r bd1 and r bd2 is the voltage subtracted the forward voltage drop, v f , of dz bd from the flyback voltage, e rev1 , of the auxi liary winding, d . the quasi - resonant signal, e rev2 , on the bd pin , is the voltage divided the former voltage by r bd1 and r bd2 . the delay time, t ondly , is adjusted by e rev2 and c bd . af ter the power mosfet turns off, while the quasi - resonant signal increases to the quasi - resonant opera tion thres hold voltage 1, v bd(th1) = 0.24 v , the power mosfet remains off . after that, when e rev2 decreases enough to cross the quasi - resonant opera tion
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 14 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 threshold voltage 2, v bd(th2) = 0.17 v , the power mosfet turns on again. in addition, at this point, the threshold voltage automatically increases to v bd(th1) to prevent malfunction of the quasi - resonant operation from noise interference. r bd1 and r bd2 setup r bd1 and r bd2 must set the range for the quasi - resonant signal , v bd(th1) = 0.34 v(max.) or more under input and output con ditions where v cc becomes lowest, but less than the absolute ma ximum rating of the bd pin, 6.0 v, under conditions where v cc becomes highest. the target voltage of e rev2 is about 3.0v, and the effective pulse width must be 1.0s or more between the two p oints v bd(th1) = 0.34 v (max.) and v bd(th2) = 0.27 v (max.) c bd setup the delay time, t ondly , after which the power mosfet turns on, is adjusted by the value of c bd , so that the power mosfet turns on a t the bot tom - on of v ds as shown in figure 8 - 12 , while th e power mosfet drain voltage, v ds , the drain current , i d , and the quasi - resonant signal, under the maximum input voltag e and the maximum output power . an initial reference value for c bd is about 1000pf. the following show how to adjust the turn - on point: if the turn - on point precedes the bottom of the v ds signal (see figure 8 - 14 ), it causes higher switching losses. in that situation, after confi r ming the initi al turn - on point, delay the turn - on point by increasing the c bd value gradually, so that the turn - on will match the bottom point of v ds . in the converse situation, if the turn - on point lags behind the v ds bottom point (see figure 8 - 15) , it causes higher switching losses also. after confirming the initial turn - on point, advance the turn - on point by decreasing the c bd value gradually, so that the turn - on w ill match the bottom point of v ds . 2 4 gnd v cc bd st ocp 8 7 6 c 1 d 2 r 2 c 2 t 1 d p r ocp c v q 1 r bd 2 r bd 1 dz bd c bd e rev 2 e in e fly e in flyback voltage forward voltage 0 e fw 1 e rev 1 hp on auxiliary winding voltage waveform e rev 2 0 v bd ( th 1 ) v bd ( th 2 ) clamping snubber u1 r 12 c 9 about 3 . 0 v recommended , but less than 6 . 0 v acceptable bd pin voltage waveform r st figure 8 - 13. bd p in p eripheral c ircuit ( l eft) and a uxiliary w inding v oltage ( r ight)
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 15 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 figure 8 - 14. when the t urn - on of a v ds w aveform o ccurs af ter a b ottom p oint figure 8 - 15. when the t urn - on of a v ds w aveform o ccurs after a b ottom p oint 8.3.3. bd pin blanking time figure 8 - 16 shows two different bd pin waveforms, comparing tr ansformer coupling conditions between the primary and second ary winding. the poor coupling tends to happen in a low output voltage transformer design with high n p /n s turns ratio (n p and n s indicate the number of turns of the primary winding and secondary w inding, respectively), and it results in high leakage inductance. the poor coupling causes high surge voltage ringing at the power mosfet drain pin when it turns off. that high surge voltage ringing is coupled to the auxiliary winding and then the inapprop riate quasi - resonant signal occurs. the bd p in has a blanking period of 250 ns( max.) to avoid the ic reacting to it, but if the surge voltage period continues that value or more , the ic responds to it and repeatedly turns the power mosfet on and off at high frequency. th is result in an increase of the mosfet power dis sipation and temperature, and the power mosfet can be damaged. the following adjustments are required when such high frequency operation occurs . c bd must be connected near the bd pin and the gn d pin . the circuit trace loop between the bd pin and the gnd pin must be separated from any traces carrying high current . the coupling of the primary winding and the auxiliary winding must be good . the clamping snubber circuit ( see figure 8 - 13 ) must be ad justed properly. e rev 2 e rev 2 normal waveform ( good coupling ) inappropriate waveform ( poor c oupling ) v bd ( th 1 ) = 0 . 24 v v bd ( th 2 ) = 0 . 17 v bd pin blanking time 250 ns ( max .) v bd ( th 1 ) = 0 . 24 v v bd ( th 2 ) = 0 . 17 v figure 8 - 16. t he difference of bd pin voltage waveform by the coupling condition of the transformer; good coupling (left) versus inappr opriate coupling (right)
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 16 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 8.3.4. bottom skip quasi - resonant operation in order to reduce switching losses during light to medium load conditions, in addition to quasi - resonant operation, the bottom skip function is built in, to limit the rise of the power mosfet o peration frequency. this function monitors the power mosfet drain current (in fact, the ocp pin voltage), it automatically changes to normal quasi - resonant operation during heavy load conditions , and it also changes to bottom skip quasi - r esonant operation during light to medium loads. figure 8 - 17 shows the operation state transition diagram of the output load from light load to heavy load. figure 8 - 18 shows that from heavy load to light load. as t hese are state change diagrams without input compensation of ocp , the overcurrent detection threshold voltage shows just a v ocp(h) = 0.910 v . this ic has a built - in automatic multi - mode control which changes among the following three operational modes according to t he output loading state: auto standby mode, one bottom - skip quasi - resonant operation, and normal quasi - resonant operation. the mode is changed from one bottom - skip quasi - resonant operation to normal qua si - resonant operation ( figure 8 - 17 ), when load is increased from one bottom - skip operation, the mosfet peak drain current value increase s , the on - time widens, and thus the peak value of the ocp pin voltage increases. when the load is increased further and the ocp pin voltage increase s to v ocp(bs1) , the mode is changed to normal quasi - resonant operation. the mode is changed from normal quasi - resonant operation to one bottom - skip quasi - resonant operation ( figure 8 - 18 ), when load is reduced from normal quasi - res onant operation, the mosfet peak drain current value decrease s , the on - time shortens, and thus the peak value of the ocp pin voltage decreases. when the load is reduced further and the ocp pin voltage decreases to v ocp(bs2) , the mode is changed to one bott om - skip quasi - resonant operation. this suppresses the rise of the operation frequency. figure 8 - 17. operation state transition diagram from light load to heavy load conditions figure 8 - 18. operation state transition diagram from heavy load to light load conditions
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 17 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 as shown in figure 8 - 19 , in the process of the increase and decrease of load current, hysteresis is imposed at the time of each operational mode change. for this reason, the switching waveform does not become unstable near the threshold voltage of a change, and this enables the ic to switch in a stable operation. one bottom - skip quasi - resonant normal quasi - resonant v ocp ( bs 2) v ocp ( bs 1) v ocp (h) load current figure 8 - 19. hysteresis at the time of an operational mode change figure 8 - 20 shows the effective pulse width of quasi - resonant signal waveform under lig ht load condition. in order to perform stable normal quasi - resonant operation and one bottom - skip operation, it is necessary to ensure that the pulse width of the quasi - resonant signal is 1 .0 s or more under the con ditions of minimum input voltage and minimum output power. the pulse width of the quasi - r esonant signal, e rev2 , is defined as the interval between v bd(th1) = 0.34 v ( max. ) on the rising edge, and v bd(th2) = 0.27 v( max. ) on the fallin g edge of the pulse. ocp pin voltage e rev 2 v bd ( th 1) = 0.34v( max .) pulse width 1.0 s or more v bd ( th 2) = 0.27v( max .) (a) normal quasi - resonant operation ocp pin voltage e rev 2 v bd ( th 1) = 0.34v( max .) v bd ( th 2) = 0.27v( max .) pulse width 1.0 s or more (b) one bottom - skip quasi - resonant operation figure 8 - 20. effective pulse width of a quasi - resonant signal 8.4. auto standby function the auto standby function automatically changes the ic operation mode to standby mode with burst oscillation, when the mosfet drain current, i d , decreases during light loads. the ocp pin circuit monitors i d . when the o cp pin voltage decreases to the standby state threshold voltage (about 9% compared to v ocp(h) = 0.910 v) , the auto standby function change s switching mode to standby mode ( see figure 8 - 21 ). the burst oscillation mode is controlled , so that when the fb/olp pin voltage decreases to v fb(stbop) , the ic stops switching operation, and when it increases to that value or more, the ic starts switching operation. because the burst oscillation mode has a certain interval of off - time, switchin g losses are reduced and efficiency is improved under light load conditions. generally, a burst interval is set to several kilohertz or less, in order to improve the efficiency during light loads. in this low frequency, audible noise may occur from the tr ansformer. however, this ic keeps the peak drain current low during burst oscillation mode, and suppresses the audible noise of the transformer further by enabling the step - on burst oscillation function, which expands the pulse width gradually. during the transition stage to burst oscillation mode, if the v cc pin voltage decreases to the start up current supply threshold volt age, v cc(bias) = 11.0v, the bias assist function is activated. because this function provides the start up current , i cc(startup ) to the v cc pin, in order to prevent the fall of the v cc pin voltage , it enables stable standby operation. if the bias assist function operates during normal operation (which includes burst oscillation mode periods) , the power consumption of the ic increase s. the refore, in order to always keep the v cc pin voltage more than v cc(bias) , it is necessary to adjust the turn ratio between the auxiliary winding and secondary winding of the transformer, and /or minimiz e the value of r2 shown in figu re 8 - 5 .
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 18 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 normal operation standby operation normal operation burst oscillation output current , i out drain current , i d below several khz figure 8 - 21. auto standby m ode t iming 8.5. overvoltage protection (ovp) when the voltage between the v cc pin and gnd pin increases to the ovp operation thresh old voltage , v cc(ovp) = 31. 5 v, the overvoltage protection function (ovp) is activated and stops switching operation . while the ovp function is active, because the bias assist function is disabled, the v cc pin voltage decreases to v cc(off) = 9.4v . because t he uvlo (undervoltage lockout) circuit becomes active, the control circuit stops operation, and the ic reverts to the state before startup. then, when the v cc pin voltage increases due to the startup current and reaches v cc(on) = 15.1v, the control circuit returns to normal operation again. in this way, the intermittent oscillation mode is operated by the uvlo circuit repeatedly while there is an excess voltage condition. by this intermittent oscillation, stress on components, such as the power mosfet and t he secondary rectifier diode, is reduced. furthermore, because the switching period is shorter than an oscillation stop period, power consumption under intermittent operation can be minimized. when the fault condition is removed, the ic returns to normal o peration automatically. when the auxiliary winding supplies the v cc pin voltage, the ovp function is able to detect an excessive output voltage, such as when the detection circuit for output control is open on the secondary side, because the v cc pin voltag e is proportional to the output voltage. the output voltage of the secondary side at ovp operation, v out(ovp) , is calculated approximately as follows: ) v ( .5 31 ) operation normal ( v ) operation normal ( v v cc out out(ovp) = ( 3 ) 8.6. overload protection ( olp ) when the drain peak current is limited by ocp oper ation, the output voltage, v out , decreases and the feedback current from the secondary photo - coupler, i fb (see figure 8 - 22 ), becomes z ero . as a result, the fb/olp pin voltage increases , charging the capacitor c4, until this voltag e increases to v fb(max) = 4.05v. after that, the capacitor c4 is charged by i fb(olp) = ? 10a. when the fb/olp pin voltage increases to v fb(olp) = 5.96v, the ic stops switching operation. when the olp function is activated, the bias assist function is disabled, as mentioned in section 8.5 , and intermittent mode op eration by the uvlo circuit is performed repeatedly. when the fault condition is removed, the ic returns to normal operation automatically. the time o f the fb/olp pin voltage from v fb (max ) = 4.05v to v fb(olp) = 5.96v is defined as the olp delay time, t dly . because the capacitor c3 for phase compensation is small com pared to c4, in the case of i fb(olp) = ? 10a, the approximate value of t dly is det ermined as follows : ( ) ) olp ( fb ) max ( fb ) olp ( fb dly i 4 c v v t ? ( ) a) ( 10 4 c ) v ( 05 . 4 ) v ( 96 . 5 = ( 4 ) in the case of c4 = 4.7f, the value of t dly would be approxi mately 0.9s. the recommended value of r1 is 47k.
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 19 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 8 1 fb / olp gnd i fb c4 c3 r1 pc 1 v cc pin voltage fb / olp pin voltage v fb ( olp ) = 5.96v v fb ( max ) = 4.05v v cc (on ) drain current , i d t dly charged by i fb ( olp ) v cc ( off ) u1 figure 8 - 22. olp operation waveforms (left) and fb/olp pin peripheral circuit (right) 8.7. thermal shutdown (tsd) if the temperature of the ic reaches more than the thermal shutdown temperature t j (tsd) = 135c (min.) , the thermal shutdown function (tsd) is activate d, and the ic stops switching operation. when the tsd function is activated, the bias assist function is disabled, as mentioned in section 8.5 , and intermittent mode operat ion by the uvlo circuit is performed repeatedly. when the fault condition is removed, the ic returns to normal operation automatically. 8.8. overcurrent protection (ocp) t he overcurrent prote ction circuit (ocp) detects each peak drain current of the power mosf et on pulse - by - pulse basis, by the current detection resistor, r ocp . when the ocp pin voltage reaches the ocp threshold, the ic turns off the power mosfet and limits the output power. 8.8.1. overcurrent input compensation function when using a quasi - resonant conv erter with universal input (85 to 265 vac), if the output power is set constant, then because higher input voltages have higher frequency, the mosfet peak drain current becomes low. because r ocp is fixed, the ocp point in the higher input voltage will shif t furth er into the overload area. t hus, the output current at ocp point in the maximum input voltage, i out(ocp) , approximately doubles relative to that in the minimum input voltage (see the curve of i out without input compensation of figure 8 - 23) . in order to suppress this phenomenon, this ic has the overcurrent input compensation function. as for determining an input compensation value, it is necessary to avoid excessive input compensation for the output current specification, i out . when excessive input compensation is applied, i out(ocp) may be below i out in the situation where the input voltage is high. therefore, it is necessary to ensure that i out(ocp) remains more than i out across the full range of input voltage , such as the cu rve of i out with appropriate input compensation in figure 8 - 23. figure 8 - 23. ocp circuit input compensation figure 8 - 24 shows an overcurrent input compensation circuit, and figure 8 - 25 shows e fw1 and e fw2 relative to the input voltage. also, figure 8 - 26 shows the relationship between the overcurrent thresh old voltage s after inp ut compensation, v ocp(h) ', and the bd pin voltage, e fw2 . the overcurrent input compensation function
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 20 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 compensates the overcurrent detection threshold voltage (normal opera tion), v ocp(h) , according to the input voltage. t he forward voltage, e fw1 , is proport ional to the input voltage, the voltage passed through dz bd from e fw1 is biased by either end of r bd1 and r bd2 , and thus the bd pin voltage is provided the voltage on r db2 divided by the divider of r bd1 and r bd2 . figure 8 - 26 show s the relationship between the overcurrent detection threshold voltage after input voltage compensation, v ocp(h) ' , and e fw2 . read t he value of v ocp(h) ' according to e fw2 in figure 8 - 26. dz bd setting: the starting voltage for inpu t compensation is set by the zener voltage, v z , of dz bd . according to the input voltage specification or transformer specification, it is required to be v z = 6.8 to 30 v. r bd1 setting: see section 8.3.2 the recommended value of r bd2 : 1.0 k overcurrent input compensation should be adjusted so that the va riance of the output current, i out(ocp) , at an ocp point, is minimized at the high and low input voltage. in addition, the input compensation must be adjusted so that i out(ocp) r emains more than the output current specification, i out , across the full range of input voltage , such as the curve of i out with appropriate input compensation in figure 8 - 23. if v ocp(h) ' is compensated to t he bottom - skip operation thresh old voltage, v ocp(bs1) , or less, the ic will change from one bottom - skip operation to normal quasi - resonant operation, and thus will raise the operation frequency and will provide output power. therefore, switching losses in normal quasi - resonant op eration is higher than that in bottom - skip operation. in this case, when the input compensation is compensated to v ocp(bs1) or less, the temperature of the power mosfet should be checked in normal quasi - resonant operation switched from bottom - skip operatio n, by changing load condition. e fw2 , which includes surge voltage, must be within the absolute maximum rating of the bd pin voltage ( ? 6.0 to 6.0 v) at the maximum input voltage. 2 gnd v cc bd ocp 8 7 6 d2 r2 c2 t1 d r ocp r bd 2 r bd 1 dz bd c bd the voltage divided the forward voltage by resistors , e fw 2 flyback voltage , e rev 1 forward voltage , e fw 1 v dzbd u1 r12 c9 figure 8 - 24. overcurrent i nput c ompensation c ircuit e fw 1 e fw 2 100v 230v ac ac 0 0 v z ocp input compensation starting point : the point matching , e fw 1 ?v z = 0v figure 8 - 25. e fw1 and e fw2 v oltage r elative to ac i nput v oltage figure 8 - 26. overcurrent t hreshold v oltage after i nput c ompensation, v ocp(h) ' ( r eference for d esign t arget v alues) ? ? ? ? ? ? (v) bd p in v oltage , e fw2 (v) m ax. t yp. m in. v ocp(h) =0.910 : recommended use range
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 21 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 figure 8 - 27 shows each voltage waveform for the input voltage in normal quasi - resona nt operation . point a : v dzbd e fw1 e fw2 will be produced negative voltage, and the detection voltage for an overcurrent event is the overcurrent detection threshold voltage (normal operation), v ocp(h) . point b t o point d : v dzbd < e fw1 when the input voltag e increas e s and e fw1 exceeds the zener voltage, v z , of d zbd , e fw2 will be produced as a negative voltage to compensate the overcurrent detection threshold voltage (normal operation), v ocp(h) . e fw2 is generally adjusted to the bd pin voltage of e fw2 = ? 3.0v at the maximum input voltage. adjustment of e fw2 will change the overcurrent detection threshold voltage by an overcurrent input compensation function. therefore, e fw2 must be adjusted while checking the input compensation starting point and the amount of input c ompensation. also, the variations of the overcurrent detection threshold voltage after input compensation, v ocp(h) ', can be calculated by the minimum and maximum values shown in figure 8 - 26. 8.8.2. reference bd pin peripheral components se tting this example demonstrates the determination of external component values for the bd pin peripheral circuit. it assumes universal input (85 to 265 vac) is being used, and input compensation begin s from the input voltage of 120 vac. the transformer is assumed to have primary winding with n p = 40 t, and an auxiliary winding with n d = 5 (turn) . to determine the zener voltage, v z , of d zbd , e fw1 at 120vac is cal culated as follows : e fw 1 = n h n t v mr ( ac ) ( 5 ) = 5 turn 40 turn 120 vac 2 = 21 . 2 v . the zener diode rating, v z , is chosen to be 22 v, a standard value. r bd1 results in e fw2 = ? 3.0v at the maximum input voltage of 265vac, as follows: r bd 1 = r fh 6 | e du 5 | l n h n t v mr ( ac ) ? bd ? | e du 6 | p ( 6 ) = 1 k | ? 3 v | ? 5 turn 40 turn 265 vac 2 ? 22 v ? | ? 3 v | ? = 7 . 28 k
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 22 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 the r bd1 rating is chosen to be 7.5k of the e series. choosing r bd2 = 1.0 k, the | e fw2 | value at 265vac can be calculated as follows: e fw 2 = r fh 6 r fh 5 + r fh 6 ( | e du 5 | f z fh ) ( 7 ) = 1 k 7 . 5 k + 1 k ? 5 turn 40 turn 265 vac 2 ? 22 v ? = 2 . 92 k k, r bd1 = 7.5 k, v f = 0.7 v, and e rev1 = 20 v, e rev2 of figure 8 - 13 can be calculated as follows: e fw 2 = r fh 6 r fh 5 + r fh 6 ( e pct 5 f v j ) ( 8 ) = 1 k 7 . 5 k + 1 k ( 20 v ? 0 . 7 v ) = 2 . 27 v . in this case, the quasi - resonant voltage e rev2 meets the design guidelines: it is quasi - resonant operation threshold voltage 1 , v bd(th1) = 0.24 v or more, and e fw2 and e rev2 are kept within the limits of the absolute maximum rating ( ? 6.0 v to 6.0 v) of the bd pin. 8.8.3. reference example of no overcurrent in put compensation required when the input voltage is narrow range, or provided from a pre - regulator such as pfc of active filter, the variation of t he input voltage is small. thus , the variation of ocp point may become less than that of the universal input voltage specification. when overcurrent input compensation is not required, the input compensation function can be disabled by substituting a high - speed diode for the zener diode ( dz bd ) , and by keeping the bd pin voltage from being negative voltage. in ad dition, the following formula shows the reverse voltage of a high - speed diode. the high - speed selection should take account of its derating. e fw 1 = n h n t maximum input voltage ( 9 ) 8.9. maximum on - time limitation function when the input voltage is lo w or in a transient state such that the input voltage turns on or off, the on - time of the power mosfet is limited to the m aximum o n - t ime, t on(max) = 40.0s ( see figure 8 - 28 ). t hus, the peak drain current is limited, and the audibl e noise of the transformer is suppressed. in designing a power supply, the on - time must be less than t on(ma x) . if such a transformer is used that the on - time is t on(max ) or more, under the condition with the minimum input voltage and the maximum output pow er, the output power would become low. in that case, the transformer should be redesigned taking into consideration the followin g: inductance, l p , of the transformer should be lowered in order to raise the operation frequency. lower the primary a nd the sec ondary turns ratio, n p /n s , to lower the duty cycle. v ds i d rg rg rg 8.10. drv pin peripheral components figure 8 - 29 shows the per ipheral circuit around drv pin. the drv pin is the gate drive pin for driving the external power mosfet. t he output voltage, v drv , is 7.5 v (min.), the peak source current and peak sink current are ? 150ma and 608ma, respectively. it is necessary to choose the external power mosfet of which the gate threshold voltage, v gs(th) is less than v drv enough across the full temperature range in the application. r4, r5, and d3 should be adjusted considering po wer losses of the power mosfet, gate waveform (reduction of ringing caused by pattern layout, and others), and emi noise, based on actual operation in the application. r3 prevents malfunctions caused by steep dv/dt at turning off the power mosfet. i t is re commended to place a resistor of 10k to 100k close to gate and source of the power mosfet.
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 23 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 drv 5 u1 d3 r5 r4 r3 r ocp gnd 8 figure 8 - 29. drv p in p eripheral c ircuit 9. design notes 9.1. peripheral components take care to use properly rated and proper typ e of components . input and ou tput electrolytic capacitor apply proper design margin to ripple current, voltage, and temperature rise. use of high ripple current and low impedance types, designed for switch - mode power supplies, is recommended, depending on their purposes. transformer apply proper design margin to core temperature rise by core loss and copper loss. because switching currents contain high frequency currents, the skin effect may become a consideration. in consideration of the skin effect, choos e a suitable wire gauge in consideration of rms current and a current density of about 3 to 4a/mm 2 . if measures to further reduce temperature are still necessary, the following should be considered to increase the total surface area of the wiring: - increase the number of wires in parallel. - use litz wires. - thicken the wire gauge. current detection resistor, r ocp a high frequency switching current flows to r ocp , and may cause poor operation if a high inductance resistor is used. choose a low inductance and hig h surge - tolerant type. 9.2. transformer design the design of the transformer is fundamentally the same as the power transformer of a ringing choke converter (rcc) system: a self - excitation type flyback converter. however, because the duty cycle will cha nge due to the quasi - resonant operations delaying the turn - on, the duty cycle needs to be compensated. when the on - duty, d on , is calculated by the ratio of the primary turns, n p , and the secondary turns, n s , the inductance, l p ' on the primary side, taking into consideration the delay time, can be cal culated by equation (10). t1 s e in n p n s l p c v e fly i d i off v o c6 v f c1 d4 p figure 9 - 1 . quasi - resonant c ircuit ( ) 2 v 0 on ) min ( in 1 0 o 2 on ) min ( in p c f d e f p 2 d e ' l ? ? ? ? ? ? ? ? + = ( 10 ) where : p o is t he maximum output power, f o is the minimum operation frequency of quasi - resonant operation , c v is the voltage resonance capacitor connected between the drain and source of the power mosfet, 1 is the transformer efficiency, d on is the on - du ty at the minimum input voltage : fly ) min ( in fly on e e e d + = ( ) f o s p fly v v n n e + =
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 24 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 each parameter, su ch as the peak drain current, i dp , is calculated as follows : v p ondly c ' l t = ( ) ondly 0 on on t f 1 d ' d ? = = = ? = 2 is the conversion efficiency of the power supply , i dp is the peak drain current d on ' is the on - duty after compensation, and v o is the secondary side output voltage the minimum operation frequency of quasi - resonant operation , f o , can be calculated by equation (17) in transformer design, al - value and n p must be set in a way that the ferrite core does not saturate. here, use ampere turn value (at), the result of i dp n p and the graph of ni - limit (at) versus al - value ( figure 9 - 2 is an example of it). ni - limit is the limit that the ampere turn value should not exceed; otherwise the core saturates. when choosing a ferrite core to match the relationship of ni - limit (at) versus al - value, it is recommended to set the calculated ni - l imit value below about 30% from the ni - limit curve of ferrite core data, as shown in the hatched area containing the design point in figure 9 - 2 , to provide a design margin in consideration of temperature effects and other variatio ns. ( ) ' l c d e 4 p 2 p 2 f ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? =
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 25 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 9.3. protection against negative input voltage at start - up pin if the st pin volta ge is applied more negative voltage than ? 0.3v, the ic may be out of normal operation, and thus e ither a diode or a resistor must be added , as shown in figure 9 - 3 . the diode or resistor should be chosen in the following specificat ion. in addition , it is necessary to check the operation based on actual operation across the full range of input voltage in the application. c 1 d 2 r 2 c 2 t 1 d p v cc gnd st 4 8 7 u 1 add a resistor or a diode drv e in r st figure 9 - 3 . st pin countermeasure ag ainst negative applied voltage the recommended specification of additional diode or resistor - the case of resistor, r st type of resistors, such as metal oxide film . the minimum value: 5.6 k the maximum value: meet equation (18). ? i cc ( startup ) ( min . ) ? st + v wxevx ( on ) ( max . ) ? e in ( min . ) ( 18) where: i cc(startup) ( min. ) is ? 4.5ma , v start(on) ( max. ) is 24 v , and e in ( min. ) is the c1 voltage at the minimum input voltage . the value of r st i n universal input range (85 vac to 265vac) is 5.6 k to 15 k . - diode characteristics peak reverse voltage , v rm : > 35 v forward current , i f : > 4 .5 ma reverse recovery time , t rr: <27 s reverse current , i r : <100 a 9.4. phase compensation a typical phase compensat ion circuit with a secondary shunt regulator (u2) is shown in figure 9 - 4 . the value of c7 is recommended to be about 0.047 f to 0.47 f, and should be chosen based on actual operation in the application. place c3 between the fb/olp pin and the gnd pin, as shown in figure 9 - 5 , to perform high frequency noise reduction and p hase compensation. the value of c3 is recommended to be about 470 pf to 0.01 f, and should be chosen based on actual operation in the appl ication. t1 d4 c6 r6 r7 u2 r9 r11 c7 s pc 1 r8 r10 l1 c8 v out gnd figure 9 - 4 . peripheral circuit around secondary shunt regulator ( u2 ) pc 1 c3 8 1 fb / olp gnd u1 i fb figure 9 - 5 . fb/olp per ipheral circuit
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 26 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 9.5. pcb trace layout and component placement pcb design and component layout significantly affect operation, emi noise, and power dissipation. therefore, pay extra attention to these designs. in general, where high frequency current traces form a loop, as shown in figure 9 - 6 , wide, short traces, and small circuit loops are important to reduce line impedance. in addition, earth ground traces affect radiated emi noise, and the same measures should be taken into account. switch - mode power supplies consist of current traces with high frequency and high voltage, and thus trace design and component layouts should be done to comply with all safety guidelines. furthermore, because the power mosfet has a positive thermal coefficient of r ds(on) , consider it when preparing a thermal de sign. figure 9 - 6 . high f requency c urrent l oops ( h atched a reas) figure 9 - 7 shows a circuit layout design example. ic p eripheral c ircuit (1) power mosfet and ocp trace layout: ocp pin to power mosfet source to r ocp to c1 to t1(p winding) to power mosfet drain this is the main trace containing switching currents, and thus it should be as wide and short as possible. if c1 and the ic are distant from each other, an electrolytic capacitor or film capacitor (about 0.1f and with proper voltage rating) near the ic or the transformer is recommended to reduce impedance of the high frequency current loop. (2) gnd trace layout: the gnd pin to c2 (negative pin) to t1 (windin g d) to r2 to d 2 to c2 (positive pin) to v cc pin . this trace also must be as wide and short as possible. if c2 and the ic are distant from each other, placing a capa citor (approximately 0.1 f to 1.0 f film capacitor) close to the v cc pin and the gnd pin is recommended. (3) r ocp trace layout r ocp should be placed as close as possible to the peripheral components of ocp pin. the connection between the power ground of main trace and the control circuit ground should be connected by a sin gle point ground ( point a i n figure 9- 7 ) to remove common impedance, and to avoid interference from switching currents to the control circuit. secondary rectifier trace layout: t1(s winding ) to d 4 to c 6 this trace should be as wide as possible. if the loop distance is lengthy, leakage inductance resulting from the long loop may increase surge voltage at turnin g off the power mosfet. proper se condary trace layout helps to increase margin against the power mosfet breakdown voltage, and reduces stress on the cl amp snubber circuit and losses in it.
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 27 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 d 2 r 2 c 2 t 1 d p pc 1 c 4 c v 1 2 4 gnd v cc bd fb / olp st ocp 8 7 6 5 ssc 1 s 311 a c 3 r bd 2 r bd 1 dz bd c bd r 1 c 1 r ocp d 3 r 5 r 4 r 3 d 4 c 6 s main power circuit trace gnd trace for the ic drv a secondary rectifier trace r 12 c 9 c 5 u 1 r st figure 9 - 7 . peripheral c ircuit e xample around the ic (SSC1S311A)
SSC1S311A SSC1S311A - dse rev. 1.3 sanken electric co., ltd. 28 dec. 22, 2 01 7 h ttp://www.sanken - ele.co.jp/en ? s anken e lectric c o ., l td. 2012 important notes all data, illustrations, graphs , tables and any other information included in this document (the ? information ? ) as to sanken? s products listed herein (the ? sanken products?) are current as of the date this document is issued . the information is subject to any change without notice due to improvement of the s anken products , etc. please make sure to confirm with a sanken sales representative that the contents set forth in this document reflect the latest revisions before use. the sanken products are intended for use as components of general purpose electronic e quipment or apparatus (such as home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). prior to use of the sanken products, please put your signature, or affix your name and seal, on the specification documents of the sa nken products and return them to sanken. when considering use of the sanken products for any applications that require high er reliability (such as transportation equipment and its control systems, traffic signal control systems or equipment , disaster/crime alarm systems, various safety devices, etc.), you must contact a sanken sales representative to discuss the suitability of such use and put your signature, or affix your name and seal, on the specification documents of the sanken products and return them to sanken, prior to the use of the sanken products. the sanken products are not intended for use in any applications that require extremely high reliability such as: aerospace equipment; nuclear power control systems; and medical equipment or systems, whos e failure or malfunction may result in death or serious injury to people, i.e., medical devices in class iii or a higher class as defined by relevant laws of jap an (collectively, the ?specific applications?). sanken assumes no liability or responsibility w hatsoever for any and all damages and losses that may be suffered by you, users or any third party, resulting from the use of the sanken products in the specific applications or in manner not in compliance with the instructions set forth herein. in the eve nt of using the sanken p roducts by either (i) combining other products or materials or both therewith or (ii) physically, chemically or otherwise processing or treating or both the same , you must duly consider all possible risks that may result from all su ch uses in advance and proceed therewith at your own responsibility. although sanken is making efforts to enhance the quality and reliability of its products, it is impossible to completely avoid the occurrence of any failure or defect or both in semicondu ctor products at a certain rate. you must take, at your own responsibility , preventative measures including using a sufficient safety design and confirming safety of any equipment or systems in/for which the sanken products are used, upon due consideration of a failure occurrence rate and derating, etc., in order not to cause any human injury or death, fire accident or social harm which may result from any failure or malfunction of the sanken products. please refer to the relevant specification documents an d sanken ? s official website in relation to derating. no a nti - radioactive ray design ha s been adopted for the sanken p roducts. the c ircuit constant , operation examples, circuit examples, pattern layout examples, design examples , recommended examples , all in formation and evaluation results based thereon, etc., described in this document are presented for the sole purpose of refere nce of use of the sanken products . sanken assume s no responsibility whatsoever for any and all damages and losses that may be suffe red by you, users or any third party, or any possible infringement of any and all property rights including intellectual property rights and any other rights of you, u sers or any third party , result ing from the information . no information in this document can be transcribed or copied or both without sanken?s prior written consent. regarding the information, no license, express, implied or otherwise, is granted hereby under any intellectual property rights and any other rights of sanken. unless otherwise agr eed in writing between sanken and you, sanken makes no warranty of any kind, whether express or implied, including, without limitation, any warranty (i) as to the quality or performance of the sanken products (such as implied warr anty of merchantability, a nd implied warranty of fitness for a particular purpose or special environment), (ii) that any sanken product is delivered free of claims of third parties by way of infringement or the like, (iii) that may arise from course of performance , course of dealin g or usage of trade, and (iv) as to the information (includ ing its accuracy, usefulness, and reliability). in the event of using the sanken products, you must use the same after carefully examining all applicable environmental laws and regulations that reg ulate the inclusion or use or both of any particular controlled substances, including , but not limi ted to , the eu rohs directive , so as to be in strict compliance with such applicable laws and regulations . you must not use the sanken products or the inform ation for the purpose of any military applications or use, including but not limited to the development of weapons of mass destruction. in the event of exporting the sanken products or the information , or providing them for non - residents, you must comply w ith all applicable export control laws and regulations in each country including the u.s. export administration regulations (ear) and the foreign exchange and foreign trade act of japan , and follow the procedures required by such applicable laws and regula tions. sanken assumes no responsibility for any troubles, which may occur during the transportation of the sanken products including the falling thereof, out of sanken?s distribution network. although sanken has prepared this document with its due care to pursue the accuracy thereof, sanken does not warrant that it is error free and sanken assumes no liability whatsoever for any and all damages and losses which may be suffered by you resulting from any possible error s or omissions in connection with the inf ormation . please refer to our official website in relation to general instructions and directions for us ing the sanken products , and refer to the relevant specification documents in relation to particular precautions when using the sanken products. all rig hts and title in and to any specific trademark or tradename belong to sanken and such original right holder(s). dsgn - cez - 1600 3

▲Up To Search▲

Price & Availability of SSC1S311A

	To Download SSC1S311A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .